1. Field of Application
The present invention relates to a test circuit to be built into a semiconductor integrated circuit having an internal bus, for use in testing the internal bus.
2. Prior Art Technology
In general, a semiconductor integrated circuit (referred to the following simply as an integrated circuit) of a type having one or more internal buses such as an address, data bus, etc, is configured as a number of function modules within the integrated circuit chip. These function modules are mutually interconnected by the internal buses, and a function module will in general be connected between an internal bus and external pads (i.e. which are external to the integrated circuit chip and which are connected to the external pins of the integrated circuit), for use in transferring data etc. between the bus and external circuits. Usually, testing of such an integrated circuit is executed by applying a test pattern to the external pins of the integrated circuit, and the operation of the integrated circuit chip as a whole and also the operation of each of the function modules is thereby checked. FIG. 1 shows an example of a prior art integrated circuit having one internal bus designated by numeral 4 and three function modules I, II and III which are mutually interconnected via the internal bus 4. The integrated circuit further includes respective test circuits 5, 6 and 7 for the function modules I, II and III, and also a test circuit 8 for the internal bus 4. The internal bus 4 consists of a set of parallel data lines for respective bits of an address or a data word (e.g. 16 lines in the case of 16 bits), and a corresponding set of external pads 10 are provided which are connected to the function module III. These external pads 10 can be used both during normal operation of the integrated circuit and also for test purposes. The internal bus test circuit 8 is provided with a dedicated set of external pads 9, i.e. which are used only when testing the internal bus 4.
The purpose of the internal bus test circuit 8 is to enable the respective bit values of the lines of the internal bus 4 to be monitored, or to set these bit values as required for the purpose of testing the bus. It is thereby possible to detect the presence of open-circuits or short-circuits in the internal bus 4, by methods which are well known in the art and so will not be described in detail herein.
However with such a prior art integrated circuit, if faults occur within a plurality of the function modules, or within a plurality of lines of the internal bus, then it may be extremely difficult to detect and locate the faults by using the external pads 9 and 10, i.e. by monitoring or applying test signals to the external pins that are connected to these pads. In particular, when a fault occurs on an internal bus which interconnects a number of function modules, it is difficult to distinguish between a fault within a function module and a fault within the bus itself. Moreover, although a dedicated test circuit such as the test circuit 8 may be provided for an internal bus, the test circuits of the function modules have priority in the test operations, i.e. the main test objectives are to check the operation of each of the function modules. If a dedicated test circuit is also provided for an internal bus (or a number of dedicated test circuits, in the case of a plurality of internal buses), then the overall chip area is accordingly increased and may become excessively large, and the overall configuration of the integrated circuit may become excessively complex. In addition, the coupling of such an additional test circuit to each internal bus will result in an increased level of bus transmission delay. Furthermore, faults may arise in the test circuits themselves.
With a prior art integrated circuit having a dedicated test circuit for an internal bus, as illustrated in FIG. 1, it is necessary to provide a set of dedicated external pads, for use only in bus testing. Hence, the total number of pins of the integrated circuit will be accordingly increased. Moreover, as stated above, the testing of the function modules usually takes priority over testing of an internal bus or internal buses. It will therefore generally be necessary to use a test method whereby the test data for the internal buses are temporarily held, so that it is difficult to directly test the internal bus by real-time operation.